1. Field of the Invention
The present invention relates to a DQPSK (Differential Quaternary Phase Shift Keying) delay detection circuit and in particular to a DQPSK delay detection circuit for materializing a low power consumption and minimizing the circuit size.
2. Description of the Prior Art
FIG. 4 is a block diagram showing the structure of the DQPSK delay detection circuit reported in "Proceeding of The 1990 IEICE Fall Conference; B-300 Constitution and characteristics of p/4 shift QPSK baseband delay detector".
This DQPSK delay detection circuit 51 comprises a semi-synchronous detector 2, low-pass filter 3, A-D convertor 4, data delay unit 55, operation unit 56, judging unit 7, and clock pulse generator 58.
The data delay unit 55 has a shift register T'. The clock pulse generator 58 is provided with a clock signal generation circuit 9 and BTR (Bit Timing Recovery) 60.
The clock signal generation circuit 9 of the clock pulse generator 58 supplies a 32f clock signal, a signal with a frequency 32 times as high as the symbol rate frequency f, to the A-D convertor 4, data delay unit 55, and operation unit 56. The BTR 60 of the clock pulse generator 58 supplies a 2f clock signal, a signal with a frequency two times as high as the symbol rate frequency f, to the judging unit 7.
In the above mentioned DQPSK delay detection circuit 51, semi-synchronous detector 2 synchronously detects an input signal, the obtained in-phase detection output X and orthogonal detection output Y is passed through the low-pass filter 3, the A-D convertor 4 samples the outputs X and Y at a frequency 32 times as high as the symbol rate frequency f, and performs an analog to digital conversion with six quantization bits. The shift register T' of the data delay unit 55 delays the output of the A-D convertor 4 by a time equivalent to the one time slot.
In the next step, the present output of the A-D convertor 4 and the one-time-slot-before output, delayed by the data delay unit 55, of the same is computed to obtain orthogonal signals I and Q containing a code bit information. Further, BTR (Bit Timing Recovery) 60 of the clock pulse generator 58, regenerates a 2f clock signal on the basis of the timing of the code bit of the signal Q outputted from the operation unit 56, the judging unit 7 selects a point with the largest eye aperture among 32 sample points in one time slot on the basis of the regenerated 2f clock signal, in-phase signal and orthogonal signal modulations and parallel-serial conversions are performed before outputing the data.
In the above explained conventional DQPSK delay detection circuit 51, each of the units (A-D convertor 4, data delay unit 55, and operation unit 56) on the way to the operation unit 56 performs high-speed processing at the 32f frequency, which is 32 times as high as the symbol rate frequency f, till the BTR 60 of the clock pulse generator 58 regenerates a 2f clock signal on the basis of the timing of the code bit of the signal Q.
There occurs a drawback that the power consumption increases because the high-speed processing is performed at a frequency 32 times as high as the symbol rate frequency f.
Assuming the number of quantization bits in the A-D convertor 4 as m and the ratio of the sampling frequency to the symbol rate frequency (=sampling frequency/symbol rate frequency) in the shift register T' of the data delay unit 55 as n, 2 mn flip flops are required for the shift register T' of the data delay part 55 in general. Because the above embodiment according to the prior art requires "2.times.6.times.32" flip flops, a problem occurs that a large shift register T' becomes necessary and thereby a decrease of circuit size is difficult.